Field of the Invention
The present invention relates to a thin film transistor, and more particularly, to a thin film transistor in a backplane substrate of a display device including the same.
Discussion of the Related Art
The development of various portable electronic appliances, such as mobile communication terminals and laptop computers, is increasing the demand for flat panel display devices that may be applied to such portable electronic appliances.
As examples of flat panel display devices, liquid crystal display devices, plasma display panel devices, field emission display devices, and organic or inorganic light emitting diode display devices are being studied. Among these examples of flat panel display devices, the application fields of liquid crystal display devices and organic light emitting diode display devices are expanding owing to several advantages including the development of mass production technology, ease in driving means, low power consumption, and the realization of high resolution and a large screen.
The flat panel display devices described above may include a plurality of pixels arranged in a matrix with one or more thin film transistors (TFTs) provided in each pixel so as to individually control the corresponding pixel. The thin film transistors may be categorized as a top gate type or a bottom gate type based on the position of a gate electrode.
FIG. 1 is a cross sectional view illustrating a typical top gate type TFT after the formation of a gate electrode. In the typical top gate type TFT, amorphous silicon layer is first formed on a substrate 10, and is crystallized using an excimer laser so as to form polysilicon.
Subsequently, a photosensitive film (not illustrated) is applied on the crystallized polysilicon, and is then subjected to exposure and developing processes to form a photosensitive film pattern. As the polysilicon is etched using the photosensitive film pattern as a mask, as illustrated in FIG. 1, an active layer 20 remains at a designed location on each pixel.
However, the above crystallization is typically conducted at a temperature of 400° C. or more. In this process, protrusions may be formed at the locations at which grains grown in the active layer 20 meet each other. Once the thin film transistor is formed in this manner and the power is applied to it, an electric field may be concentrated at the protrusions, which may undesirably reduce a breakdown voltage, thus causing an undesired leakage of current. In addition, during the manufacture process, the protrusions make the thin film transistor more vulnerable to electrostatic defects, thus causing a reduction in the production yield. This disadvantage may be exacerbated when the thickness of a gate insulating layer is reduced in newer generation of devices in the interests of realizing low power consumption and a slim design.
After the active layer 20 is formed in the typical top gate type TFT, a gate insulating layer 30 and a gate electrode 40 are formed in sequence. In this case, the gate insulating layer 30 and the gate electrode 40 cover the protrusions of the active layer 20. Thus, the protrusions formed on the surface of the active layer 20 result in protrusions at the respective interfaces of the gate insulating layer 30 and the gate electrode 40.
The active layer 20 has a channel formed in a portion thereof that overlaps the gate electrode 40. The gate insulating layer 30 is interposed between the active layer 20 and the gate electrode 40. Thus, the channel is formed at a non-uniform interface between the active layer 20 and the gate insulating layer 30 caused by the protrusions at the surface of the active layer 20 described above. This may lead to high hot carrier stress (HCS), resulting in deterioration in reliability.